APTRANSCO STUDY MATERIAL | 8086 MICROPROCESSOR OVERVIEW | Indian Shout

You are here: » APTRANSCO STUDY MATERIAL | 8086 MICROPROCESSOR OVERVIEW

APTRANSCO STUDY MATERIAL | 8086 MICROPROCESSOR OVERVIEW

8086 MICROPROCESSOR ARCHITECTURE | 8086 MICROPROCESSOR PIN DIAGRAM | BASICA OF MICROPROCESSOR 8086 | APTRANSCO PREPARATION MATERIAL | APTRANSCO STUDY NOTES

HI FRIENDS THIS MATERIAL COURSE GIVE OVERVIEW OF 8086 MICROPROCESSOR USED FOR ALL EXAMS

8086 MICROPROCESSOR

8086 FEATURES:

•It is a 16-bit µp.

•8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).

•It can support up to 64K I/O ports.

•It provides 14, 16 -bit registers.

•It has multiplexed address and data bus AD0- AD15 and A16 – A19.

•It requires single phase clock with 33% duty cycle to provide internal timing.

•8086 is designed to operate in two modes, Minimum and Maximum.

•It can prefetches upto 6 instruction bytes from memory and queues them in order to

speed up instruction execution.

•It requires +5V power supply.

•A 40 pin dual in line package

Minimum and Maximum Modes:

•The minimum mode is selected by applying logic 1 to the MN / MX  input pin. This is a

single microprocessor configuration.

•The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a

multi micro processors configuration.

8086 PIN-DIAGRAM

8086 MICROPROCESSOR PIN DIAGRAM

SIGNAL GROUPS OF 8086 MICROPROCESSOR

ARCHITECTURE OF 8086

8086 MICROPROCESSOR BLOCK DIAGRAM ARCHITECTURE

Internal Architecture of 8086

•8086 has two blocks BIU and EU.

•The BIU performs all bus operations such as instruction fetching, reading and writing

operands for memory and calculating the addresses of the memory operands. The

instruction bytes are transferred to the instruction queue.

•EU executes instructions from the instruction system byte queue.

•Both units operate asynchronously to give the 8086 an overlapping instruction fetch and

execution mechanism which is called as Pipelining. This results in efficient use of the

system bus and system performance.

•BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.

•EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,

Flag register.

BUS INTERFACE UNIT:

•It provides a full 16 bit bidirectional data bus and 20 bit address bus.

•The bus interface unit is responsible for performing all external bus operations.

Specifically it has the following functions:

•Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and

Bus control.

•The BIU uses a mechanism known as an instruction stream queue to implement a

pipeline architecture.

•This queue permits prefetch of up to six bytes of instruction code. When ever the queue

of the BIU is not full, it has room for at least two more bytes and at the same time the EU

is not requesting it to read or write operands from memory, the BIU is free to look ahead

in the program by prefetching the next sequential instruction.

•These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the

BIU fetches two instruction bytes in a single memory cycle.

•After a byte is loaded at the input end of the queue, it automatically shifts up through the

FIFO to the empty location nearest the output.

•The EU accesses the queue from the output end. It reads one instruction byte after the

other from the output of the queue. If the queue is full and the EU is not requesting access

to operand in memory.

•These intervals of no bus activity, which may occur between bus cycles are known as

Idle state.

•If the BIU is already in the process of fetching an instruction when the EU request it to

read or write operands from memory or I/O, the BIU first completes the instruction fetch

bus cycle before initiating the operand read / write cycle.

•The BIU also contains a dedicated adder which is used to generate the 20bit physical

address that is output on the address bus. This address is formed by adding an appended

16 bit segment address and a 16 bit offset address.

•For example: The physical address of the next instruction to be fetched is formed by

combining the current contents of the code segment CS register and the current contents

of the instruction pointer IP register.

•The BIU is also responsible for generating bus control signals such as those for memory

read or write and I/O read or write.

EXECUTION UNIT :

The Execution unit is responsible for decoding and executing all instructions.

•The EU extracts instructions from the top of the queue in the BIU, decodes them,

generates operands if necessary, passes them to the BIU and requests it to perform the

read or write bys cycles to memory or I/O and perform the operation specified by the

instruction on the operands.

•During the execution of the instruction, the EU tests the status and control flags and

updates them based on the results of executing the instruction.

•If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted

to top of the queue.

•When the EU executes a branch or jump instruction, it transfers control to a location

corresponding to another set of sequential instructions.

•Whenever this happens, the BIU automatically resets the queue and then begins to fetch

instructions from this new location to refill the queue.

Module 1 and learning unit 4:

Signal Description of 8086•The Microprocessor 8086 is a 16-bit CPU available in

different clock rates and packaged in a 40 pin CERDIP or plastic package.

•The 8086 operates in single processor or multiprocessor configuration to achieve high

performance. The pins serve a particular function in minimum mode (single processor

mode) and other function in maximum mode configuration (multiprocessor mode ).

•The 8086 signals can be categorised in three groups. The first are the signal having

common functions in minimum as well as maximum mode.

•The second are the signals which have special functions for minimum mode and third

are the signals having special functions for maximum mode.

The following signal descriptions are common for both modes.

AD15-AD0: These are the time multiplexed memory I/O address and data lines.

• Address remains on the lines during T1 state, while the data is available on the data bus

during T2, T3, Tw and T4.

•These lines are active high and float to a tristate during interrupt acknowledge and local

bus hold acknowledge cycles.

A19/S6,A18/S5,A17/S4,A16/S3: These are the time multiplexed address and status

lines.

•During T1 these are the most significant address lines for memory operations.

•During I/O operations, these lines are low. During memory or I/O operations, status

information is available on those lines for T2,T3,Tw and T4.

•The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.

•The S4 and S3 combinedly indicate which segment register is presently being used for

memory accesses as in below fig.

•These lines float to tri-state off during the local bus hold acknowledge. The status line

S6 is always low.

•The address bit are separated from the status bit using latches controlled by the ALE

signal.

S4 S3 INDICATION
0

0

1

1

0

1

0

1

ALTERNATE DATA

STACK

CODE OR ALONE

DATA

•/S7: The bus high enable is used to indicate the transfer of data over the higher

order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-

D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is

low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be

transferred on higher byte of data bus. The status information is available during T2, T3

and T4. The signal is active low and tristated during hold. It is low during T1 for the first

pulse of the interrupt acknowledges cycle.

BHE A0 INDICATION
0

0

1

1

0

1

0

1

Whole word

Upper byte from or to odd address

Lower byte from or to even address

None

•RDRead: This signal on low indicates the peripheral that the processor is performing s

memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of

any read cycle. The signal remains tristated during the hold acknowledge.

•READY: This is the acknowledgement from the slow device or memory that they have

completed the data transfer. The signal made available by the devices is synchronized by

the 8284A clock generator to provide ready input to the 8086. the signal is active high.

•INTR-Interrupt Request: This is a triggered input. This is sampled during the last

clock cycles of each instruction to determine the availability of the request. If any

interrupt request is pending, the processor enters the interrupt acknowledge cycle.

•This can be internally masked by resulting the interrupt enable flag. This signal is active

high and internally synchronized.

•TEST:This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low,

execution will continue, else the processor remains in an idle state. The input is

synchronized internally during each clock cycle on leading edge of clock.

•CLK- Clock Input: The clock input provides the basic timing for processor operation

and bus control activity. Its an asymmetric square wave with 33% duty cycle.

•MN/MX : The logic level at this pin decides whether the processor is to operate in either

minimum or maximum mode.

•The following pin functions are for the minimum mode operation of 8086.

•M/ IO  – Memory/IO: This is a status line logically equivalent to S2 in maximum mode.

When it is low, it indicates the CPU is having an I/O operation, and when it is high, it

indicates that the CPU is having a memory operation. This line becomes active high in

the previous T4 and remains active till final T4 of the current cycle. It is tristated during

local bus “hold acknowledge “.

• INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt

acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.

•ALE – Address Latch Enable: This output signal indicates the availability of the valid

address on the address/data lines, and is connected to latch enable input of latches. This

signal is active high and is never tristated.

•DT/R  – Data Transmit/Receive: This output is used to decide the direction of data

flow through the transreceivers (bidirectional buffers). When the processor sends out

data, this signal is high and when the processor is receiving data, this signal is low.

•DEN – Data Enable: This signal indicates the availability of valid data over the

address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to

separate the data from the multiplexed address/data signal. It is active from the middle of

T2 until the middle of T4. This is tristated during ‘ hold acknowledge’ cycle.

•HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the

processor that another master is requesting the bus access.

•The processor, after receiving the HOLD request, issues the hold acknowledge signal on

HLDA pin, in the middle of the next clock cycle after completing the current bus

cycle.

•At the same time, the processor floats the local bus and control lines. When the

processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an

asynchronous input, and is should be externally synchronized.

•If the DMA request is made while the CPU is performing a memory or I/O cycle, it will

release the local bus during T4 provided:

1.The request occurs on or before T2 state of the current cycle.

2.The current cycle is not operating over the lower byte of a word.

3.The current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A Lock instruction is not being executed.

•The following pin function are applicable for maximum mode operation of 8086.

•S2, S1, S0 – Status Lines: These are the status lines which reflect the type of operation,

being carried out by the processor. These become activity during T4 of the previous cycle

and active during T1 and T2 of the current bus cycles.

8086 MICROPROCESSOR MAX MODE STATUS LINES

•LOCK This output pin indicates that other system bus master will be prevented from

gaining the system bus, while the LOCK signal is low.

•The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until

the completion of the next instruction. When the CPU is executing a critical instruction

which requires the system bus, the LOCK prefix instruction ensures that other processors

connected in the system will not gain the control of the bus.

•The 8086, while executing the prefixed instruction, asserts the bus lock signal output,

which may be connected to an external bus controller.

•QS1, QS0

– Queue Status: These lines give information about the status of the code-

prefetch queue. These are active during the CLK cycle after while the queue operation is

performed.

•This modification in a simple fetch and execute architecture of a conventional

microprocessor offers an added advantage of pipelined processing of the instructions.

•The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6-

bytes) instruction can be prefetched from the memory and stored in the prefetch. This

results in a faster execution of the instructions.

•In 8085 an instruction is fetched, decoded and executed and only after the execution of

this instruction, the next one is fetched.

•By prefetching the instruction, there is a considerable speeding up in instruction

execution in 8086. This is known as instruction pipelining.

•At the starting the CS:IP is loaded with the required address from which the execution is

to be started. Initially, the queue will be empty an the microprocessor starts a fetch

operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd

or two bytes at a time, if the CS:IP address is even.

•The first byte is a complete opcode in case of some instruction (one byte opcode

instruction) and is a part of opcode, in case of some instructions ( two byte opcode

instructions), the remaining part of code lie in second byte.

•The second byte is then decoded in continuation with the first byte to decide the

instruction length and the number of subsequent bytes to be treated as instruction data.

•The queue is updated after every byte is read from the queue but the fetch cycle is

initiated by BIU only if at least two bytes of the queue are empty and the EU may be

concurrently executing the fetched instructions.

•The next byte after the instruction is completed is again the first opcode byte of the next

instruction. A similar procedure is repeated till the complete execution of the

program.

•The fetch operation of the next instruction is overlapped with the execution of

the current instruction. As in the architecture, there are two separate units, namely

Execution unit and Bus interface unit.

•While the execution unit is busy in executing an instruction, after it is completely

decoded, the bus interface unit may be fetching the bytes of the next instruction from

memory, depending upon the queue status.

8086 MICROPROCESSOR QS0 QS1

•RQ / 0 GT ,RQ / 1 GT  – Request/Grant: These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the

processor current bus cycle.

•Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.

•RQ/GT pins have internal pull-up resistors and may be left unconnected.

Internal Registers of 8086

•The 8086 has four groups of the user accessible internal registers. They are the

instruction pointer, four data registers, four pointer and index register, four segment

registers.

•The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the

status register, with 9 of bits implemented for status and control flags.

•Most of the registers contain data/instruction offsets within 64 KB memory segment.

There are four different 64 KB segments for instructions, stack, data and extra data. To

specify where in 1 MB of processor memory these 4 segments are located the processor

uses four segment registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with

processor instructions. The processor uses CS segment for all accesses to instructions

referenced by instruction pointer (IP) register. CS register cannot be changed directly.

The CS register is automatically updated during far jump, far call and far return

instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with

program stack. By default, the processor assumes that all data referenced by the stack

pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register

can be changed directly using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with

program data. By default, the processor assumes that all data referenced by general

registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.

DS register can be changed directly using POP and LDS instructions.

Accumulator register consists of two 8-bit registers AL and AH, which can be

combined together and used as a 16-bit register AX. AL in this case contains the low-

order byte of the word, and AH contains the high-order byte. Accumulator can be used

for I/O operations and string manipulation.

Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.

Count register consists of two 8-bit registers CL and CH, which can be combined

together and used as a 16-bit register CX. When combined, CL register contains the low-

order byte of the word, and CH contains the high-order byte. Count register can be used

in Loop, shift/rotate instructions and as a counter in string manipulation,.

Data register consists of two 8-bit registers DL and DH, which can be combined

together and used as a 16-bit register DX. When combined, DL register contains the low-

order byte of the word, and DH contains the high-order byte. Data register can be used as

a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX

register contains high-order word of the initial or resulting number.

The following registers are both general and index registers:

•Stack Pointer (SP) is a 16-bit register pointing to program stack.

•Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is

usually used for based, based indexed or register indirect addressing.

•Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register

indirect addressing, as well as a source data address in string manipulation instructions.

•Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and

register indirect addressing, as well as a destination data address in string manipulation

instructions.

Other registers:

•Instruction Pointer (IP) is a 16-bit register.

•Flags is a 16-bit register containing 9 one bit flags.

•Overflow Flag (OF) – set if the result is too large positive number, or is too small

negative number to fit into destination operand.

•Direction Flag (DF) – if set then string manipulation instructions will auto-decrement

index registers. If cleared then the index registers will be auto-incremented.

•Interrupt-enable Flag (IF) – setting this bit enables maskable interrupts.

•Single-step Flag (TF) – if set then single-step interrupt will occur after the next

instruction.

•Sign Flag (SF) – set if the most significant bit of the result is set.

•Zero Flag (ZF) – set if the result is zero.

•Auxiliary carry Flag (AF) – set if there was a carry from or borrow to bits 0-3 in the AL

register.

•Parity Flag (PF) – set if parity (the number of “1” bits) in the low-order byte of the

result is even.

•Carry Flag (CF) – set if there was a carry from or borrow to the most significant bit

during last result calculation.

Addressing Modes

•Implied – the data value/data address is implicitly associated with the instruction.

•Register – references the data in a register or in a register pair.

•Immediate – the data is provided in the instruction.

•Direct – the instruction operand specifies the memory address where data is located.

•Register indirect – instruction specifies a register containing an address, where data is

located. This addressing mode works with SI, DI, BX and BP registers.

•Based:- 8-bit or 16-bit instruction operand is added to the contents of a base register

(BX or BP), the resulting value is a pointer to location where data resides.

•Indexed:- 8-bit or 16-bit instruction operand is added to the contents of an index register

(SI or DI), the resulting value is a pointer to location where data resides

•Based Indexed:- the contents of a base register (BX or BP) is added to the contents of

an index register (SI or DI), the resulting value is a pointer to location where data resides.

•Based Indexed with displacement:- 8-bit or 16-bit instruction operand is added to the

contents of a base register (BX or BP) and index register (SI or DI), the resulting value is

a pointer to location where data resides.

Memory •Program, data and stack memories occupy the same memory space. As the

most of the processor instructions use 16-bit pointers the processor can effectively

address only 64 KB of memory.

•To access memory outside of 64 KB the CPU uses special segment registers to specify

where the code, stack and data 64 KB segments are positioned within 1 MB of memory

(see the “Registers” section below).

•16-bit pointers and data are stored as:

address: low-order byte

address+1: high-order byte

•Program memory – program can be located anywhere in memory. Jump and call

instructions can be used for short jumps within currently selected 64 KB code segment,

as well as for far jumps anywhere within 1 MB of memory.

•All conditional jump instructions can be used to jump within approximately +127 to –

127 bytes from current instruction.

•Data memory – the processor can access data in any one out of 4 available segments,

which limits the size of accessible memory to 256 KB (if all four segments point to

different 64 KB blocks).

•Accessing data from the Data, Code, Stack or Extra segments can be usually done by

prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by

default may use the ES or SS segments instead of DS segment).

•Word data can be located at odd or even byte boundaries. The processor uses two

memory accesses to read 16-bit word located at odd byte boundaries. Reading word data

from even byte boundaries requires only one memory access.

•Stack memory can be placed anywhere in memory. The stack can be located at odd

memory addresses, but it is not recommended for performance reasons (see “Data

Memory” above).

Reserved locations:

•0000h – 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer

in format segment: offset.

•FFFF0h – FFFFFh – after RESET the processor always starts program execution at the

FFFF0h address.

Interrupts

The processor has the following interrupts:

•INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using

STI/CLI instructions or using more complicated method of updating the FLAGS register

with the help of the POPF instruction.

•When an interrupt occurs, the processor stores FLAGS register into stack, disables

further interrupts, fetches from the bus one byte representing interrupt type, and jumps to

interrupt processing routine address of which is stored in location 4 * <interrupt type>.

Interrupt processing routine should return with the IRET instruction.

•NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR

interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is

stored in location 0008h. This interrupt has higher priority then the maskable interrupt.

•Software interrupts can be caused by:

•INT instruction – breakpoint interrupt. This is a type 3 interrupt.

•INT <interrupt number> instruction – any one interrupt from available 256 interrupts.

•INTO instruction – interrupt on overflow

•Single-step interrupt – generated if the TF flag is set. This is a type 1 interrupt. When the

CPU processes this interrupt it clears TF flag before calling the interrupt processing

routine.

•Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape

opcode (type 7).

•Software interrupt processing is the same as for the hardware interrupts.

ilook website
 
 

Categories:Uncategorized;Tags: , , , , , , , ,

   

10 Comments to “APTRANSCO STUDY MATERIAL | 8086 MICROPROCESSOR OVERVIEW”

  1. lucky says:

    Sir,can you please send me transco and genco study material (eee) to my email id.
    Thank you.

  2. raji says:

    Sir

    please send me the study material for telecom for aptransco preparation and also send me previous papers

  3. arni tyagi says:

    sir
    pls give me the detailed notes of micro processor as here in our city yammunanagar detailed notes of this subject micro processor are not available. im studying in 2nd year of it . so , kindly pls grant me notes of this subject

  4. atul patil says:

    hello sir
    my self is atul patil now i will studied in the second year IT we have advance mp subject so please give me the notes of that sub.

  5. rama says:

    it was really a good guide or summary about 8086 mp.
    i require complete notes includng the programs description too. can you please help me.

  6. aruna says:

    sir
    i require complete notes includng the programs description too. can you please help me.

  7. anusha.s.e says:

    it was really a good guide or summary about 8086 mp.it helps a lot to viva based questions .it would be good if you add the difference between 8086 and 8085 also in this material.once again thanks a lot.

  8. APTRANSCO STUDY MATERIAL | 8086 MICROPROCESSOR OVERVIEW | entrance … says:

    […] Read the original here: APTRANSCO STUDY MATERIAL | 8086 MICROPROCESSOR OVERVIEW | entrance … […]

  9. Padmanjali says:

    Hello Sir,

    Please send me the study material for civil for the exam aptransco and also previous papers with answers for my email id.

    Thanking You Sir,

  10. […] Read more: APTRANSCO STUDY MATERIAL | 8086 MICROPROCESSOR OVERVIEW | entrance … […]

Leave your comment here: