JAWAHARLAL NEHRU TECHNOLOGY UNIVERSITY, HYDERABAD
M .Tech. II Semester Examinations,
DESIGN FOR TESTABILITY
(Common to Embedded Systems, VLSI System Design, VLSI & Embedded Systems)

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M.Tech. – II Semester Examinations,

ALGORITHMS FOR VLSI DESIGN AUTOMATION
(Common to Digital Systems & Computer Electronics/ VLSI System Design/ VLSI & Embedded Systems)

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M.Tech. I-Semester Examinations,
DIGITAL DATA COMMUNICATIONS
(Embedded Systems, Digital System and Computer Electronics, Digital Electronics and Communication Systems, VLSI System Design and Wireless and Mobile Communication ,Electronics & Communications)

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M.Tech. I-Semester Examinations
DIGITAL SYSTEM DESIGN
(Digital System and Computer Electronics, Digital Electronics and
Communication Systems, VLSI System Design)

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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech I Semester  Examinations
COMPUTATIONAL TECHNIQUES IN MICRO ELECTRONICS
(VLSI System Design)

SEPTEMBER-2009 PAPER–(SUPPLEMENTARY)

1.a]  Explain about the impact of Fabrication Process on physical design.
b]  What are the Innovations  in Interconnects in VLSI  physical Design? Explain. What are the solutions for Issues related to Interconnects

2.a]  How are the Floor planning Algorithms classified? Explain.
b]  Explain about timing driven floor planning. What are the theoretical advancements in floor planning?

3.a]  Taking a set of blocks and set of center connecting nets, show two different placements and sketch interconnecting to powers.
b]  What is the signification of Breuen’s Algorithm? What are the object foundations of this Algorithm? Explain with an example.

4.a]  Give the flow chart for two-phase routing and explain the same.
b]  Explain about sokups’ Algorithm, & Hadlocks’ Algorithms and critically compare them.

5.a]  What are the various parameters connected with routing considerations? Explain.
b]  Compare between HVH, VHV, and unreserved layer models with an example.

6.a]  Explain about ‘Moment Methods’ used in circuit simulations techniques with an example.
b]  How sensitivity analysis is done is simulation techniques? Explain this pertaining to tunning simulation.

7.  Explain about FEM, FVM and FDM techniques taking suitable examples.

8.  Write notes on any TWO:
a)  Device Modeling and simulation
b) Process simulation
c) Layout algorithms.

MARCH-2009 PAPER–REGULAR

1.a)  Explain about scaling methods used in VLSI physical design.
b)  Discuss about the issues related to Fabrication process:
i)  Parasitic effects
ii)  Interconnect delay
iii)  Noise and cross talk.

2.a)  With the help of a graph, explain about rectangular dualization pertaining to floor planning.
b)  Explain about floor planning algorithms for mixed block and cell designs.

3.a)  How are the placement Algorithms classified? Explain.
b)  With the help of an example, explain about sequence-pair technique and draw the horizontal and vertical constraint graphs for a given sequence-pair.

4.a)  With the help of sketches, explain about grid graph model, checker board graph and channel intersection graph.
b)  Explain about Non-Rectilinear Sre i nor Tree Based Algorithm for Global Routing.

5.a)  Explain about cyclic vertical constraint problem related to detailed Routing.
b)  With the help of a sketch explain about the General River Routing problem and the corresponding Algorithm.

6.  Explain about Transient Analysis and Frequency Domain analysis methods for circuit simulation Techniques, with examples.

7.a)  What are the different techniques available for device simulation and compare them.
b)  Explain about various methods of process simulation methods and critically analyze them.

8.  Write notes on any two:
a)  Yield estimation Algorithms
b)  Synthesis of Analog ICs
c)  Moment methods.

MARCH-2008 PAPER–(REGULAR)

1.a)  Compare the Transient and frequency domain analysis with suitable examples.
b)  Explain any one method of non-linear circuit simulation technique.

2.  Explain the following:
a) FEM
b) FVM.

3.  Explain the Liao-wong Algorithm for layout compaction.

4.  Why part training algorithm is used in VLSI  physical design?  Write this algorithm with example.

5.  What are the different floor planning algorithms?  Compare them.

6.  What are the important considerations and models used in routing?  Explain them indetail.

7.  What are the main categories of global routing algorithms?  Explain them with examples.

8.a)  What are the different levels where placements of blocks occur?
b)  What are the different classes of Two Layer channel routing Algorithms?

SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)

1.a)  Discuss the simulation technique of linear circuit.
b)  Explain algorithm for implementation of non linear circuit.

2.a)  Explain frequency domain analysis to obtain the spectrum.
b)  What is sensitivity domain analysis to obtain the spectrum?

5.  What are various modelling styles used in VHDL and explain them briefly with suitable examples.

6.  Give the block diagram of a simple VLSI design cycle and explain all the steps involved in the VLSI design.

7.  Give the classification of floor planning and explain Rectangular Dualization.

8.  Write short notes on:
(i) Error estimates
(ii)  Maze Routing Algorithm.

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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech I Semester  Examinations
ELECTRONIC DESIGN AUTOMATION TOOLS
(VLSI System Design)

SEPTEMBER-2009 PAPER–(SUPPLEMENTARY)

1.a]  Discuss various data types vectors arrays, strings in VERILOG HDL with examples.
b]  What is meant Logic-gate level modeling? Explain with a suitable example.

2.a]  Distinguish between lumped delay and distributed delay with example.
b]  Explain the interpretation of VERILOG constructs.

3.  Explain the sentences design flow of VHDL.

4.a]  Draw the PSPICE model for R-2R based A/D converter.
b]  Design a two stage CE amplifier & analyze it using PSPICE (Assume the data needed.

5.a]  Explain the mixed signal simulation with example.
b]  Give in detail analysis of comparator in mixed signal VLSI design.

6.  Give an account of design entries simulation, layout tools for PCB.

7.a]  Explain in detail orcood PCB design tools.
b]  Discuss timing analysis in VHDL.

8.  Write short notes on the following:
a) Operators in VERILOG HDL.
b) Limitations of PSPICE.
c)  MODEL SIM

SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)

1.a)  What is verilog HDL? Describe the major capabilities of the verilog HDL.
b)  Describe the logic gate-level modeling capability of verilog HDL.

2.a)  Define the terms ‘Simulation’ and ‘Synthesis’ relevant to HDLs. Explain them with suitable block diagrams.
b)   Give the comparison between VHDL and verilog HDL with respect to various performance parameters.

3.a)   What are the CAD tools available for HDL simulation? Explain the procedural steps for HDL simulation using modelism simulator.
b)  How to perform timing analysis using CAD tools in HDL design with suitable example.

4.  Explain the design considerations and simulation procedure for analog-to digital converter circuit using PSICE software tool.

5.a)  Explain briefly the fundamentals of mixed signal simulator configurations.
b)  Explain the analysis of up converter using the relevant CAD environment.

6.a)   What are the various software tools available for PCB design and layout? Briefly discuss about them.
b)  Describe the procedural steps for design entry, simulation and layout for PCB design.

7.a)  Give the classification of operators in verilog HDL. Explain any two of them with suitable examples.
b)  Write a task in verilog HDL that models the behaviour of an asynchronous preset clear positive edge triggered counter.

8.  Write notes on any two of the following:
a)  PSPICE model for S/H circuit
b)  Analog and digital signal simulator configurations
c)  High speed PCB Design.

MARCH-2009 PAPER-(REGULAR)

1.  Explain in detail the different features of verilog language.

2.a)  Explain the following synthesis for VHDL
i) FSM synthesis    ii) Memory synthesis
b)  Explain in detail the following simulation
i) Switch-level    ii) Transistor-level

3.  Name different CAD tools for simulation and synthesis and explain them in detail.

4.a)  Draw the PSPICE model for sample and hold circuit and explain.
b)  Design a two stage RC coupled amplifier and analyze it using PSPICE. Assume the data needed.

5.a)  Give in detail the analysis of Up and Down converters.
b)  Explain in detail mixed signal simulator configurations.

6.  Give in detail an overview of high speed PCB design.

7.a)  Explain in detail orchad PCB design tools.
b)  Write short notes on Leonardo spectrum.

8.  Write short notes on:
a) Timing controls and delay in verilog
b) Formal verification procedure

FEBRUARY-2007 PAPER

1.a)  What are the two kinds of delays that can be specified in a procedural assignment statement?  Elaborate using an example.
b)  What is meant by Logic-gate level Modeling?  Explain with a suitable example.

2.  Explain the synthesis process in both verilog and VHDL languages with suitable block diagrams.

3.a)  What are the various CAD Tools for synthesis and simulation using HDLS with respect to different vendors?
b)  What is static timing Analysis?  Explain briefly with suitable example.

4.  Explain with suitable example, Design and Analysis of Analog and digital circuits using pspice.

5.a)  Design sample and Hold circuit using Pspice Model and explain.
b)  What are the various tools for circuit design and simulation using PSPICE?

6.a)  Explain the fundamentals of Analog, Digital and Mixed signal simulators in VLSI design.
b)  Explain the Analysis of D/A converter using Mixed Signal VLSI design.

7.  Explain with suitable example Design entry, simulation and Layout tools for PCB.

8.  Write short notes on any TWO of the following:
(a) Verilog features
(b)  Integration to CAE Environments
(c)  Introduction to orcad PCB design tools.

MARCH-2008 PAPER–(REGULAR)

1.a)  Explain various kinds of Net and Register data types
b)  State two ways by which you can over ride a parameter value at compile time.

2.a)  How are blocking assignments different from non-blocking assignments?
b)  Write verilog HDL code for decade counter using structural modeling .

3.  Model a mealy FSM with machine state as a reg variable and write a verilog code for it. Analyse synthesized netlist for this model.

4.a)  Explain various types of simulations
b)  Write short notes on:
i)  Cell models  ii)  Delay models.

5.  Draw the two stage BJT amplifier in self bias mode coupled by RC network with RS = 150Ω, coupling capacitors C1 = C2 = 10 µ F,  R1 and R2 in the first stage, R1 = 200kΩ, R2 = 50kΩ, Rc1 = 12Ω, Re1 = 3.6kΩ, Ce1 = 15 µ F.  In second stage: R1 = 120KΩ, R2 = 30kΩ, Rc2 = 6.8k , C Ω e2 = 25 µ F with Rc  = 10kΩ and VCC = 15V. Draw its
pspice  schematic and using of the pspice circuit file. Draw its frequency response circuit with Vin = 1mv (P-to-P).

6.a)  Illustrate different mixed signal simulator configuration.
b)  Draw the generic D/A converter and analyse it. What are the errors associated in D/A converter.

7.a)  Illustrate the basic steps in PCB design?
b)   Describe simulation and layout tools in PCB design

8.  Write short notes on any TWO:
a)  Important features of verilog HDL
b) Features of Modelism
c) Differences between verilog & VHDL languages.

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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech I Semester  Examinations
ANALOG IC DESIGN
(VLSI System Design)

SEPTEMBER-2009 PAPER–SUPPLEMENTARY

1.a]  Why is emitter resistor RE replaced by a constant current bias circuit in differential amplifier stage of an op-AMP?
b]  Design the dual input balanced output differential amplifier with the current mirror bias (shown below) according to the following specifications:
i) Supply voltage  Vs= ±12V
ii)  Maximum output voltage swing – 6Vpp.

2.a]  Briefly explain the need for compensating networks in op-Amps.
b]  Explain in detail about advanced current mirror compensating network.

3.a]  What is a comparator? List the important characteristics of the comparator.
b]  Explain different types of comparators with neat circuit diagrams.

4.a]  Explain about CMOS sample and Hold circuit with neat waveforms.
b]  Design a second order Butterworth low pass filter with a cutoff frequency of 500 Hz and a pass band gain of -2. Assume that a  5V ±  power supply and a CMOS clock are used. [Using MF5].

5.a]  Give the procedure of design of  Biquard switched capacitor filter. [ filter is a low pass filter].
b]  Explain the operation of switched capacitor gain circuit.

6.a]  What is difference between A/D and D/A converters? Give one application of each.
b]  Draw and explain the Nyquist rate D/A converter using binary sealed converter.

7.a]  Compare the performance of different types of D/A converters?
b]  Define the resolution, settling time and conversion time of D/A converters.
c]  Explain  the  operation  of  cycle  flash type A/D converter with a neat circuit diagram.

8.a]  Write the differences b/w continuous time and discrete time filters.
b]  Explain in detail about digital decimation filter.

MARCH-2009-PAPER–(REGULAR)

1.a)  Deduce the small signal model for an n-channel MOSFET taking into account the body effect.
b)  Justify the choice of pmos loads.

3.a)  State the limitations of single stage amplifiers.
b)  Explain in detail the design and operation of cascade current mirror. Identify the limitations and suggest remedies.

4.a)  Deduce the necessary condition that ensures zero input-offset voltage for a 2 stage OP amp.
b)  Discuss the trade offs involved in selecting the input stage as p-channel or n-channel with respect to a 2 stage OP amp.

5.  Discuss in detail the compensation of OP amp that makes it completely independent of process and temperature variations.

6.a)  Discuss in detail the design features of fully differential folded cascade op amp.
b)  Give an account of charge injection errors in connection with comparators and suggest a method to minimize the same.

7.a)  Explain the following in the context of data converters:
i)  Resolution
ii)  Offset and gain error
iii)  Accuracy
iv)  Differential non linearity error
v)  Monotonicity
b)  Explain briefly a 3 bit flash A/D converter. State the salient issues in designing flash A/D converters.

8.a)  Show that the dynamic range can be increased by over sampling.
b)  Discuss the stability and linearity issues associated with delta sigma converters.

MARCH-2008 PAPER-(REGULAR)

1.a)  Explain large signal modelling of single stage BJT amplifier with neat sketches.
b)  Explain common source amplifier with current mirror active load.

2.a)  Explain the effect of negative feedback on the frequency response of OP-AMP.
b)  Explain about cascode (or) CE-CB operational amplifier and obtain AC analysis of it.

3.a)  Explain about charge injection error.
b)  With a neat circuit diagram explain Bi-CMOS comparator.
c)  Write the comparisons between Latched and Bi-CMOS comparators.

4.a)  What is a switched capacitor filter? List important features of it. How does it differ from an analog filter?
b)  Explain the operation of Bimos sample and Hold circuit with neat waveforms.

5.a)  Explain the operation of switched capacitor circuit with neat waveforms.
b)  Briefly explain correlated double sampling techniques.

6.a)  What is Quantization Noise? Explain in detail.
b)  Explain the operation at D/A converters using Hybrid converter.

7.a)  What are the performance limitations of converters?
b)  Compare different types of A/D converters.
c)  Explain Successive Approximation A/D converter with a neat circuit diagram.

8.a)  What is over sampling? Explain over sampling with and without noise sampling.
b)  Explain in detail about Band pass over sampling converter.

FEBRUARY-2007 PAPER

2.a)  Draw the circuit of CMOS current mirror and explain its working principle.
b) Explain why source/emitter follower circuits exhibits large amounts of overshoot and ringing.

3.a)  What are the ways of improving slew rate of 2-stage CMOS opamp? And derive an expression for slew rate of CMOS opamp.
b)  Explain about various OPAMP compensation techniques.

4.a)  What is CMFB circuit? What are various methods of designing CMFB circuits? And compare them.
b)  Explain the principle of continuous time CMFB circuit.

5.a)  Briefly explain about various performance parameters of sample-and-hold circuit.
b)  Draw the circuit of switched capacitor circuit and explain its principle.

6.a)  Compare and contrast CMOS and BICMOS sample and hold circuits and their performance.
b)  Define the terms as referred to converters:
i)  offset and gain error
ii) INL error
iii) DNL error
iv)  Sampling time uncertainty.

7.a)  Prove that the sinusoidal signal has 1.76dB more power than a random signal which is uniformly distributed.
b)  Explain the principle of operation of dual slope A/D converter.

8.a)  What are the advantages of 1-bit D/A converters?
b)  Derive the component values of 1st order continuous time filter.

SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)

1.a)  Derive an expression for gm of an N-channel MOS FET operating in linear and saturation regions.
b)  Give the relative performance of CS, CG, CD amplifiers.

3.a)  State the limitations of single stage amplifiers.
b)  Explain in detail the design and operation of Wilson current mirror.

4.a)  Deduce the necessary condition that ensures zero input-offset voltage for a 2 stage OP amp.
b)  Discuss the trade offs involved in selecting the input stage as p-channel or n-channel with respect to a 2 stage OP amp.

5.)  Discuss in detail the compensation of OP amp that makes it completely independent of process and temperature variations.

6.a)  Give the significance of CMFB circuits.
b)  Give an account of charge injection errors in connection with comparators and suggest a method to minimize the same.

7.a)  Explain the following in the context of data converters:
i) Resolution
ii)  Offset and gain error
iii) Accuracy
iv)  Integral non linearity error
v) Missing codes
b)  Explain briefly a 3 bit flash A/D converter. State the salient issues in designing Flash A/D converters.

8.a)  Discuss in detail the nois shaped delta sigma modulator.
b)  Write an account of band pass over sampling converters.

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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech I Semester  Examinations
VLSI TECHNOLOGY AND DESIGN
(Common To Embedded Systems, Digital Systems & Computer Electronics, VLSI
System Design and Communication Systems)

SEPTEMBER-2009 PAPER–(SUPPLEMENTARY)

1.a)  Explain how cost and delay of a logic gate varies with different IC technologies.
b)  What are the deficiencies of MOS technology? How they can it be over come?

2.a)  Explain the principle of CMOS inverter with V-I wave forms.
b)  What is latch-up condition in CMOS circuits? How it can be eliminated.

3.a) What are λ -based design rules? Give them for each layer.
b)  Draw the stick diagram of 2-impact Ex-or gate.

4.  Explain about-nmos logic, domino logic and DCVS logic and compare them.

5.a)  What are the various simulators used for combinational logic design? Explain their need.
b)  What are different testing methods for testing combinational gate? Explain with an example.

6.a)  Distinguish between clock skew and signal skew with an example.
b)  Explain about 2-phase clouding disciplines

7.a)  Explain how clock routing design optimizes the clock skew in floor planning.
b)  What is the need for package of  a chip? Explain about  input and output pad circuits.

8.  Write short notes on any Two:
a) Hardware/ Software co-design.
b) Chip design methodologies
c) Power optimization in CMOS circuits.

MARCH-2009 PAPER–(REGULAR)

1.a)  What are the various marks used in CMOS p-well process? What is the significance of each.
b)  Compare bipolar and CMOS technologies.

2.a)  What is threshold voltage? What are various factors that influences threshold voltage.
b)  Explain the principle of BICMOS inverter.

3.a)  What are various symbols used in sticks notation? Draw the stick diagram of CMOS inverter.
b)  What are scalable design rules? Explain.

4.  What are various switch logic circuits? Compare their merits and demerits.

5.  Explain how fan-out and path delay influences delay in combinational networks.

6. Explain about 1 -φ  clocking rules for flip-flops and  2 -φ   clocking disciplies for latches.

7.  What are various floor planning methods? Explain them clearly.

8.  Write short notes on any Two:
a) Testing of sequential circuits
b) Hardware/software co-design.
c) Combinational gates an network testing.

SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)

1.a)  What are the various processes of CMOS fabrication? Illustrate the main steps in a typical n-well process.
b)  Tabulate the comparism between CMOS and Bipolar Technologies.

2.a)  Determine the Pull-up to Pull-down ratio for an nMOS inverter driven through one or more pass transistors.
b)  Draw a simple BiCMOS inverter circuit diagram and explain its operation.

3.a)  Explain about scalable Design rules related to NMOS and CMOS Technologies.
b)  With suitable diagrams explain some switch logic arrangements.

4.a)  With neat sketches describe the various Layout Design methods.
b)  Explain the clocking Analysis related to sequential systems.

5.a)  With relevant diagrams explain about various Floorplanning methods used in Layout design.
b)  Explain the design Methodology for IBM ASICs.

6.a)  Give the device structure for CMOS inverter and explain the same.
b)  Draw Latch-up circuit model and explain its operation.

7.a)  Briefly explain an important issues in system-on-chip design.
b)  Write notes on Architecture Testing related Architecture VLSI Design.

8.  Write notes on any Two of the following:
a)  Wires and Vias
b)  Design validation and Testing.
c)  The Integrated circuit (IC) Era.

FEBRUARY-2007 PAPER

1.a)  Give advantages of CMOS over bipolar technologies
b)  Explain in detail the electrical model of a MOS transistor
c)  Discuss the BICMOS process

2.a)  What are the effects of scaling of Vt?
b)  Cascaded inverters can drive large capacitive loads – explain how
c)  What are the design rules? Why is metal – metal spacing larger they poly-poly spacing?

3.a)  Explain the delay in combinational logic network and how combinational delay can be reduced.
b)  Compute the zero delay signal probabilities for all signals in the network shown

4.a)  What  is  clock skew? Explain how clock skew affects the digital system. What is the maximum allowable skew for the parameters   T =10 ns, tpr = 1 ns, tsr = 1 ns, tsl = 1 ns, tpl = 5 ns, tp = 5 ns.  What is the minimum allowable clock period under these conditions?
b)  What is ATPG? DFT? Generate a set of Sequential tests for the “01” – string recognizer which test for all stuck – at – 0/1 faults, assuming you don’t know the initial state.

5.  Design a Booth Multiplier
a)  Design the logic for one bit of a adder substractor (leaf cell)
b)  Design a stick diagram for the adder substractor

6.a)  Give routing techniques to equalize channel utilization
b)  What are the problems presented by power distribution? How are they solved?
c)  Discuss the clock distribution strategies for VLSI system.
d)  How many output pads can be supported by 10λ wide power line in pad ring?

7.a)  Give a generic IC design flow chart and explain.
b)  Explain the technology independent and technology dependant strategies of logic optimization used in logic synthesis
c)  Explain briefly how the hardware/software Co-simulation and co- synthesis issued are addressed.

8.a)  How would you translate a register transfer structure into a legal 2-phase latched sequential machine?
b)  Write short notes on any two of the following:
i)  Differentiate the devices PAL, PLA and FPGA
ii) Cross-talk
iii)  Placement and routing in floor planning.

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M.TECH SYLLABUS | JNTU M.TECH SYLLABUS | JNTU SYLLABUS | JNTU M.TECH SYLLABUS BOOK | MTECH VLSI SYSTEM DESIGN SYLLABUS BOOK | JNTU M.TECH VLSI SYLLABUS BOOK | M.TECH SYLLABUS BOOKS

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, HYDERABAD

M.Tech—VLSI SYSTEM DESIGN—COURSE STRUCTURE

FIRST SEMESTER

• VLSI Technology & Design

• Digital System Design

• Analog IC Design

• Electronic Design Automation Tools

Elective –I

• Computational Techniques in Micro Electronics

• Digital Data Communications

• CPLD and FPGA Architecture and Applications
  

Elective –II

• VHDL Modeling of Digital Systems

• Modelling and Synthesis with Verilog HDL

• Embedded Systems Concepts

• HDL Programming & EDA Tools Laboratory

SECOND SEMESTER

• Algorithms for VLSI Design Automation

• Design for Testability

• Low Power VLSI Design

• Scripting Language for VLSI Design Automation
  

Elective-III

• Hardware Software Co-Design

• System Modeling & Simulation

• Network Security and Cryptography
  

Elective-IV

• DSP Processors and Architectures

• Advanced Operating Systems

• Advanced Computer Architecture

• Mixed Signal   Laboratory

THIRD  & FOURTH SEMESTERS

• SEMINAR

• PROJECT

DOWNLOAD SYLLABUS BOOK IN .PDF FORMAT

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