**DIGITAL ELECTRONICS MULTIPLE CHOICE QUESTIONS -PART-3**

**51.RAM can be expanded to a**

a. increase word size

b. increase word number

c. increase word size or increase word number

d. none of above

**52. Which memory is available in all technologies**

a. PROM

b. EEPROM

c. ROM

d. EPROM

**53. Which memory does not require programming equipment**

a. PROM

b. EEPROM

c. ROM

d. EPROM

**54. In CCD**

a. small charge is deposited for logical 1

b. small charge is deposited for logical 0 or 1

c. small charge is deposited for logical 0 and large charge for logical 1

d. none of above

**55. The internal structure of PLA is similar to**

a. RAM

b. ROM

c. both RAM or ROM

d. neither RAM nor RAM

**56.An output of combinational ckt depends on**

a. present inputs

b. previous inputs

c. both present and previous

d .none of above

**57.Which are combinational gates**

a. NAND & NOR

b. NOT & AND

c. X-OR & X-NOR

d. none of above

**58.. As access time is decreased, the cost of memory**

a. remains the same

b. increases

c. decreases

d. may increase or decrease

**59. Which is correct:**

a. A.A=0

b. A+1=A

c. A+A=A’

d. A’.A’=0

**60.A counter is a**

a. Sequential ckt

b. Combinational ckt

c. both combinational and sequential ckt

d. none of above

**61.The parity bit is**

a. always 1

b. always 0

c.1 or 0

d.none of above

**62.In 2 out of 5 code,decimal number 8 is**

a.11000

b.10100

c.1100

d.1010

63.In number of information bits is 11,the number of parity Bits in hamming code is

a.5

b.4

c.3

d.2

**64.For a 4096*8 EPROM ,the number of address lines is**

a.14

b.12

c.10

d.8

**65. 23.6 10=……….2**

a.11111.10011

b.10111.10011

c.00111.101

d.10111.1

**66.BCD number 0110011=…….10**

a.66

b.67

c.68

d.69

**67.The total number of input states for 4 input or gate is**

a.20

b.16

c.12

d.8

**68.In a 4 input OR gate,the total number of High outputs for the 16 input states are**

a.16

b.15

c.13

d. none of above

**69.In a 4 input AND gate,the total number of High outputs for the 16 input states are**

a.16

b.8

c.4

d.1

**70.a buffer is**

a. always non-inverting

b.always inverting

c. inverting or non-inverting

d.none of above

**71.An AND gate has two inputs A and B and ine inhibits input S.Output is 1 if**

a.A=1,B=1,S=1

b. A=1,B=1,S=0

c. A=1,B=0,S=1

d. A=1,B=0,S=0

**72. An AND gate has two inputs A and B and ine inhibits input S.Out of total 8 input states,Output is 1 in**

a. 1 states

b. 2 states

c. 3 states

d. 4 states

**73.In a 3 input NOR gate,the number of states in which output is 1 equals**

a. 1

b. 2

c. 3

d. 4

**74.Which of these are universal gates**

a. only NOR

b. only NAND

c. both NOR and NAND

d. NOT,AND,OR

**75. In a 3 input NAND gate,the number of gates in which output in 1equals**

a.8

b.7

c.6

d..5

**76. A XOR gate has inputs A and B and output Y.Then the output equation is**

a.Y=A+B

b.Y=AB+A’B

c.AB+ AB’

d.AB’+A’B’

**77.A 14 pin NOT gate IC has………..NOT gates**

a.8

b.6

c.5

d.4

**78.A 14 pin AND gate IC has………..AND gates**

a.8

b.6

c.4

d.2

**79.The first contribution to logic was made by**

a. George Boole

b. Copernicus

c. Aristotle

d. Shannon

**80.Boolean Alzebra obeys**

a. commutative law

b. associative law

c. distributive law

d. commutative, associative, distributive law

**81. A+(B.C)=**

a. A.B+C

b. A.B+A.C

c. A

d.(A+B).(A+C)

**82.A.0=**

a. 1

b. A

c. 0

d. A or 1

**83.A+A.B=**

a. B

b. A.B

c. A

d. A or B

84.Demorgan’s first theorem is

a. A.A’=0

b. A’’=A

c. (A+B)’=A’.B’

d. (AB)’=A’+B’

**85. Demorgan’s second theorem is**

a. A.A’=0

b. A’’=A

c. (A+B)’=A’.B’

d. (AB)’=A’+B’

86. Which of the following is true

a. SOP is a two level logic

b. POS is a two level logic

c. both SOP and POS are two level logic

d. Hybrid function is two level logic

**87.The problem of logic race occurs in**

a. SOP functions

b. Hybrod functions

c. POS functions

d. SOP and POS functions

88. In which function is each term known as min term

a. SOP

b. POS

c. Hybrid

d. both SOP and POS

89. In which function is each term known as max term

a. SOP

b. POS

c. Hybrid

d. both SOP and Hybrid

**90. In the expression A+BC, the total number of min terms will be**

a.2

b. 3

c.4

d. 5

**91.The min term designation for ABCD is**

a.m0

b. m10

c. m14

d. m15

**92. The function Y=AC+BD+EF is**

a. POS

b. SOP

c. Hybrid

d. none of above

93. The expression Y=∏M(0,1,3,4) is

a. POS

b. SOP

c. Hybrid

d. none of above

**94. AB+AB’=**

a. B

b. A

c.1

d. 0

**95. In a four variable Karnaugh map eight adjacent cells give a**

a. Two variable term

b. single variable term

c. Three variable term

d. four variable term

**96.A karnaugh map with 4 variables has**

a. 2 cells

b. 4 cells

c. 8 cells

d.16 cells

97.In a karnaugh map for an expression having ‘don’t care terms’ the don’t cares can be treated as

a. 0

b. 1

c. 1 or 0

d. none of above

**98. The term VLSI generally refers to a digital IC having**

a. more than 1000 gates

b. more than 100 gates

c. more than 1000 but less than 9999 gates

d. more than 100 but less than 999 gates

**99.Typical size of an IC is about**

a.1”*1”

b. 2”*2”

c. 0.1”*0.1”

d. 0.0001”*0.0001”

100.A digital clock uses…………..chip

a. SSI

b. LSI

c. VLSI

d. MSI

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answers of above questions which i think .

53-c

56-c

57-b

58-b

64-b

67-b

68-b

69-d

71-a

72-a

73-a

74-c

75-b

76-Y=AB’=A’B

77-d

78-c

79-a

81-b

82-c

84-c

85-d

88-a

89-b

90-a

91-d

92-b

93-a

94-b

95-b

96-d

97-c

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