Code No. B6806
JAWAHARLAL NEHRU TECHNOLOGY UNIVERSITY, HYDERABAD
M .Tech. II Semester Supplementary Examinations, March – 2009
ALGORITHMS FOR VLSI DESIGN AUTOMATION
(Common to Digital Systems & Computer Electronics, VLSI System
Design and VLSI & Embedded Systems)
Time: 3 hours Max.Marks.60
Answer any Five questions
All questions carry equal marks
1.a) Explain the process of generic IC Design methodology.
b) Explain briefly the term ‘Computational Complexity’ related to Algorithms for
VLSI design Automation.
2.a) Explain briefly the general purpose methods for combinational optimization.
b) Write short notes on Genetic Algorithms.
3.a) Explain the concept of placement with respect to layout synthesis.
b) Explain the routing problems in floor planning methods of VLSI design.
4. What is meant by modeling and simulation? Differentiate grate level and switch
level modeling and simulation procedures with suitable example.
5.a) Discuss the basic issues and terminology employed in logic synthesis in VLSI
b) Explain about two-level logic synthesis with suitable example.
6.a) Explain about assignment and scheduling relevant to High-level Logic synthesis.
b) Write short notes on High-level transformations related High-level logic
7.a) With suitable diagram explain physical design cycle for FPGAs.
b) Write short notes on FPGA technologies.
8.a) Explain partitioning, placement and routing related to physical design automation
b) Write short notes on MCM physical design cycle.