Code No: NR-54211/MT
M.Tech. II-Semester Examinations, July/August – 2006.
DESIGN OF FAULT TOLERANT SYSTEMS
(Common to Digital Systems and Computer Electronics and
Digital Electronics and Communication Systems)
Time: 3 hours Max. Marks: 60
Answer any FIVE questions
All questions carry equal marks
– – –
1.a) Define Reliability and Failure rate and derive the relationship
between these two parameters.
b) Discuss about the reliability of series-parallel and parallel –
2.a) With a neat diagram explain the principle of operation of sift out
modular redundancy (SMR). Give its merits and demerits.
b) Explain in detail about Time redundancy and Software
3.a) Design a totally self checking checker using m-out-of-n codes.
b) Design a totally self checking checker using low cost residue
4.a) Discuss about the fail safe design of sequential circuits using
b) Discuss about totally self checking PLA design.
5.a) With a neat diagram, explain the Reed-Muller’s expansion
b) Discuss about the use of control and syndrome testable design.
6.a) With a neat diagram explain how an LFSR is used as signature
b) Discuss in detail about the working of multiple-input signature
7.a) Using necessary diagrams, explain the principle of operation of
level sensitive scan design (LSSD)
b) Explain controllability and observability by means of scan
8.a) Distinguish between BIST exhaustive testing, pseudorandom
testing and pseudo exhaustive testing. Give examples.
b) Explain in detail about generic offline BIST architecture.