Download JNTU (OR) M.TECH 2-Semester DESIGN OF FAULT TOLERANT SYSTEMS JULY/AUG-2006 Exam Question Paper | Indian Shout

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Download JNTU (OR) M.TECH 2-Semester DESIGN OF FAULT TOLERANT SYSTEMS JULY/AUG-2006 Exam Question Paper

Code No: OR-21/DECS
OR
M.Tech. II-Semester Examinations, July/August-2006.
DESIGN OF FAULT TOLERANT SYSTEMS
(Digital Electronics and Communication Systems)
Time: 3 hours                   Max. Marks: 60
Answer any FIVE questions
All questions carry equal marks

– – –
1.a)  Define reliability and MTBF.  Derive the relationship between these two
parameters.
b)  With neat diagrams discuss about reliability of series and parallel
systems.

2.a)  Explain the basic principle of path sensitization, with an example.  For
the circuit given below, derive the test vectors to detect SAD and SAI
faults at node ‘h’

DESIGN OF FAULT TOLERANT SYSTEMS OR-JULY-AUG-2006

b)  With an example, explain the basic principle of transition count testing.
Also give its merits and demerits.

3.a)  Distinguish between static, dynamic and Hybrid redundancy techniques
in their implementation.
b)  With a neat diagram explain the principle of operation of 5MR (Five
modular redundancy) reconfiguration scheme.

4.a)  Discuss in detail about Time and software redundancy schemes.
b)  Give some examples of practical fault Tolerant systems and explain
about them briefly.

5.a)  Design a totally self checking checker using m-out-of n codes.
b)  Discuss briefly about partially self checking circuits.

6.a)  Discuss about the fail-safe design of sequential circuits using Berger
codes.
b)  Discuss about the design of totally self-checking PLA.

7.a)  With neat diagrams discuss about the Reed-Muller expansion technique.
b)  Discuss about the use of control and syndrome-testable design.

8.a)  Discuss about the scan-path technique.
b)  Discuss about the level-sensitive scan design (LSSD).

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