# JNTU M.TECH COMPUTATIONAL TECHNIQUES IN MICRO ELECTRONICS-(CTME) QUESTION PAPERS

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M. Tech I Semester  Examinations
COMPUTATIONAL TECHNIQUES IN MICRO ELECTRONICS

(VLSI System Design)

SEPTEMBER-2009 PAPER–(SUPPLEMENTARY)

1.a]  Explain about the impact of Fabrication Process on physical design.
b]  What are the Innovations  in Interconnects in VLSI  physical Design? Explain. What are the solutions for Issues related to Interconnects

2.a]  How are the Floor planning Algorithms classified? Explain.
b]  Explain about timing driven floor planning. What are the theoretical advancements in floor planning?

3.a]  Taking a set of blocks and set of center connecting nets, show two different placements and sketch interconnecting to powers.
b]  What is the signification of Breuen’s Algorithm? What are the object foundations of this Algorithm? Explain with an example.

4.a]  Give the flow chart for two-phase routing and explain the same.
b]  Explain about sokups’ Algorithm, & Hadlocks’ Algorithms and critically compare them.

5.a]  What are the various parameters connected with routing considerations? Explain.
b]  Compare between HVH, VHV, and unreserved layer models with an example.

6.a]  Explain about ‘Moment Methods’ used in circuit simulations techniques with an example.
b]  How sensitivity analysis is done is simulation techniques? Explain this pertaining to tunning simulation.

7.  Explain about FEM, FVM and FDM techniques taking suitable examples.

8.  Write notes on any TWO:
a)  Device Modeling and simulation
b) Process simulation
c) Layout algorithms.

MARCH-2009 PAPER–REGULAR

1.a)  Explain about scaling methods used in VLSI physical design.
b)  Discuss about the issues related to Fabrication process:
i)  Parasitic effects
ii)  Interconnect delay
iii)  Noise and cross talk.

2.a)  With the help of a graph, explain about rectangular dualization pertaining to floor planning.
b)  Explain about floor planning algorithms for mixed block and cell designs.

3.a)  How are the placement Algorithms classified? Explain.
b)  With the help of an example, explain about sequence-pair technique and draw the horizontal and vertical constraint graphs for a given sequence-pair.

4.a)  With the help of sketches, explain about grid graph model, checker board graph and channel intersection graph.
b)  Explain about Non-Rectilinear Sre i nor Tree Based Algorithm for Global Routing.

5.a)  Explain about cyclic vertical constraint problem related to detailed Routing.
b)  With the help of a sketch explain about the General River Routing problem and the corresponding Algorithm.

6.  Explain about Transient Analysis and Frequency Domain analysis methods for circuit simulation Techniques, with examples.

7.a)  What are the different techniques available for device simulation and compare them.
b)  Explain about various methods of process simulation methods and critically analyze them.

8.  Write notes on any two:
a)  Yield estimation Algorithms
b)  Synthesis of Analog ICs
c)  Moment methods.

MARCH-2008 PAPER–(REGULAR)

1.a)  Compare the Transient and frequency domain analysis with suitable examples.
b)  Explain any one method of non-linear circuit simulation technique.

2.  Explain the following:
a) FEM
b) FVM.

3.  Explain the Liao-wong Algorithm for layout compaction.

4.  Why part training algorithm is used in VLSI  physical design?  Write this algorithm with example.

5.  What are the different floor planning algorithms?  Compare them.

6.  What are the important considerations and models used in routing?  Explain them indetail.

7.  What are the main categories of global routing algorithms?  Explain them with examples.

8.a)  What are the different levels where placements of blocks occur?
b)  What are the different classes of Two Layer channel routing Algorithms?

SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)

1.a)  Discuss the simulation technique of linear circuit.
b)  Explain algorithm for implementation of non linear circuit.

2.a)  Explain frequency domain analysis to obtain the spectrum.
b)  What is sensitivity domain analysis to obtain the spectrum? 5.  What are various modelling styles used in VHDL and explain them briefly with suitable examples.

6.  Give the block diagram of a simple VLSI design cycle and explain all the steps involved in the VLSI design.

7.  Give the classification of floor planning and explain Rectangular Dualization.

8.  Write short notes on:
(i) Error estimates
(ii)  Maze Routing Algorithm.

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