JNTU M.TECH ELECTRONIC DESIGN AUTOMATION TOOLS QUESTION PAPERS

JNTU M.TECH QUESTION PAPERS | JNTU QUESTION PAPERS | M.TECH QUESTION PAPERS | MTECH ELECTRONIC DESIGN AUTOMATION TOOLS QUESTION PAPERS | M.TECH VLSI QUESTION PAPERS | JNTU M.TECH PAPERS|JNTU M.TECH VLSI SYSTEM DESIGN QUESTION PAPERS


JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech I Semester  Examinations
ELECTRONIC DESIGN AUTOMATION TOOLS
(VLSI System Design)


SEPTEMBER-2009 PAPER–(SUPPLEMENTARY)

1.a]  Discuss various data types vectors arrays, strings in VERILOG HDL with examples.
b]  What is meant Logic-gate level modeling? Explain with a suitable example.

2.a]  Distinguish between lumped delay and distributed delay with example.
b]  Explain the interpretation of VERILOG constructs.

3.  Explain the sentences design flow of VHDL.

4.a]  Draw the PSPICE model for R-2R based A/D converter.
b]  Design a two stage CE amplifier & analyze it using PSPICE (Assume the data needed.

5.a]  Explain the mixed signal simulation with example.
b]  Give in detail analysis of comparator in mixed signal VLSI design.

6.  Give an account of design entries simulation, layout tools for PCB.

7.a]  Explain in detail orcood PCB design tools.
b]  Discuss timing analysis in VHDL.

8.  Write short notes on the following:
a) Operators in VERILOG HDL.
b) Limitations of PSPICE.
c)  MODEL SIM


SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)

1.a)  What is verilog HDL? Describe the major capabilities of the verilog HDL.
b)  Describe the logic gate-level modeling capability of verilog HDL.

2.a)  Define the terms ‘Simulation’ and ‘Synthesis’ relevant to HDLs. Explain them with suitable block diagrams.
b)   Give the comparison between VHDL and verilog HDL with respect to various performance parameters.

3.a)   What are the CAD tools available for HDL simulation? Explain the procedural steps for HDL simulation using modelism simulator.
b)  How to perform timing analysis using CAD tools in HDL design with suitable example.

4.  Explain the design considerations and simulation procedure for analog-to digital converter circuit using PSICE software tool.

5.a)  Explain briefly the fundamentals of mixed signal simulator configurations.
b)  Explain the analysis of up converter using the relevant CAD environment.

6.a)   What are the various software tools available for PCB design and layout? Briefly discuss about them.
b)  Describe the procedural steps for design entry, simulation and layout for PCB design.

7.a)  Give the classification of operators in verilog HDL. Explain any two of them with suitable examples.
b)  Write a task in verilog HDL that models the behaviour of an asynchronous preset clear positive edge triggered counter.

8.  Write notes on any two of the following:
a)  PSPICE model for S/H circuit
b)  Analog and digital signal simulator configurations
c)  High speed PCB Design.


MARCH-2009 PAPER-(REGULAR)

1.  Explain in detail the different features of verilog language.

2.a)  Explain the following synthesis for VHDL
i) FSM synthesis    ii) Memory synthesis
b)  Explain in detail the following simulation
i) Switch-level    ii) Transistor-level

3.  Name different CAD tools for simulation and synthesis and explain them in detail.

4.a)  Draw the PSPICE model for sample and hold circuit and explain.
b)  Design a two stage RC coupled amplifier and analyze it using PSPICE. Assume the data needed.

5.a)  Give in detail the analysis of Up and Down converters.
b)  Explain in detail mixed signal simulator configurations.

6.  Give in detail an overview of high speed PCB design.

7.a)  Explain in detail orchad PCB design tools.
b)  Write short notes on Leonardo spectrum.

8.  Write short notes on:
a) Timing controls and delay in verilog
b) Formal verification procedure


FEBRUARY-2007 PAPER

1.a)  What are the two kinds of delays that can be specified in a procedural assignment statement?  Elaborate using an example.
b)  What is meant by Logic-gate level Modeling?  Explain with a suitable example.

2.  Explain the synthesis process in both verilog and VHDL languages with suitable block diagrams.

3.a)  What are the various CAD Tools for synthesis and simulation using HDLS with respect to different vendors?
b)  What is static timing Analysis?  Explain briefly with suitable example.

4.  Explain with suitable example, Design and Analysis of Analog and digital circuits using pspice.

5.a)  Design sample and Hold circuit using Pspice Model and explain.
b)  What are the various tools for circuit design and simulation using PSPICE?

6.a)  Explain the fundamentals of Analog, Digital and Mixed signal simulators in VLSI design.
b)  Explain the Analysis of D/A converter using Mixed Signal VLSI design.

7.  Explain with suitable example Design entry, simulation and Layout tools for PCB.

8.  Write short notes on any TWO of the following:
(a) Verilog features
(b)  Integration to CAE Environments
(c)  Introduction to orcad PCB design tools.


MARCH-2008 PAPER–(REGULAR)

1.a)  Explain various kinds of Net and Register data types
b)  State two ways by which you can over ride a parameter value at compile time.

2.a)  How are blocking assignments different from non-blocking assignments?
b)  Write verilog HDL code for decade counter using structural modeling .

3.  Model a mealy FSM with machine state as a reg variable and write a verilog code for it. Analyse synthesized netlist for this model.

4.a)  Explain various types of simulations
b)  Write short notes on:
i)  Cell models  ii)  Delay models.

5.  Draw the two stage BJT amplifier in self bias mode coupled by RC network with RS = 150Ω, coupling capacitors C1 = C2 = 10 µ F,  R1 and R2 in the first stage, R1 = 200kΩ, R2 = 50kΩ, Rc1 = 12Ω, Re1 = 3.6kΩ, Ce1 = 15 µ F.  In second stage: R1 = 120KΩ, R2 = 30kΩ, Rc2 = 6.8k , C Ω e2 = 25 µ F with Rc  = 10kΩ and VCC = 15V. Draw its
pspice  schematic and using of the pspice circuit file. Draw its frequency response circuit with Vin = 1mv (P-to-P).

6.a)  Illustrate different mixed signal simulator configuration.
b)  Draw the generic D/A converter and analyse it. What are the errors associated in D/A converter.

7.a)  Illustrate the basic steps in PCB design?
b)   Describe simulation and layout tools in PCB design

8.  Write short notes on any TWO:
a)  Important features of verilog HDL
b) Features of Modelism
c) Differences between verilog & VHDL languages.


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