# JNTU MTECH VLSI TECHNOLGY & DESIGN QUESTION PAPERS | Indian Shout

You are here: » JNTU MTECH VLSI TECHNOLGY & DESIGN QUESTION PAPERS

## JNTU MTECH VLSI TECHNOLGY & DESIGN QUESTION PAPERS

JNTU M.TECH QUESTION PAPERS | JNTU QUESTION PAPERS | M.TECH QUESTION PAPERS | MTECH VLSI TECHNOLOGY AND DESIGN QUESTION PAPERS | M.TECH VLSI QUESTION PAPERS | JNTU M.TECH PAPERS

M. Tech I Semester  Examinations
VLSI TECHNOLOGY AND DESIGN
(Common To Embedded Systems, Digital Systems & Computer Electronics, VLSI
System Design and Communication Systems)

OCTOBER/NOVEMBER 2011 REGULAR EXAMINATION PAPER

1.a) Explain CMOS inverter voltage transfer characteristics with a neat diagram. What are the criteria for voltage threshold for high level and low level in inverter  characteristics?
b)  What is latch-up condition in CMOS circuits? How it can be eliminated. [12]

2.a) Determine the Pull-up to Pull-down ratio for an NMOS inverter driven through one or more pass transistors.

b) Explain about-NMOS logic, domino logic and DCVS logic and compare them.            [12]

3.a) What are the varieties of design layout of wiring trees in the wires and delay?

b) With suitable diagrams explain some switch logic arrangements.  [12]

4.a) Design the static complementary pull up and pull down networks for these expressions;

b) Draw a stick diagram for a three input NOR gate.    [12]

b)  Explain how the gate placement affects load capacitance in fanout of combinational logic.        [12]

6.a) Explain the clocking Analysis related to sequential systems.

b) Draw and explain the cross section of a pair of stacked capacitor DRAM cell.            [12]

7.a) Explain system-on-chip concept using platform based design.

b) What are the various floor-planning tips and explain it?   [12]

8.  Write a short note on a) High level synthesis.

b) ASM chart design         [12]

SEPTEMBER-2009 PAPER–(SUPPLEMENTARY)

1.a)  Explain how cost and delay of a logic gate varies with different IC technologies.
b)  What are the deficiencies of MOS technology? How they can it be over come?

2.a)  Explain the principle of CMOS inverter with V-I wave forms.
b)  What is latch-up condition in CMOS circuits? How it can be eliminated.

3.a) What are λ -based design rules? Give them for each layer.
b)  Draw the stick diagram of 2-impact Ex-or gate.

4.  Explain about-nmos logic, domino logic and DCVS logic and compare them.

5.a)  What are the various simulators used for combinational logic design? Explain their need.
b)  What are different testing methods for testing combinational gate? Explain with an example.

6.a)  Distinguish between clock skew and signal skew with an example.
b)  Explain about 2-phase clouding disciplines

7.a)  Explain how clock routing design optimizes the clock skew in floor planning.
b)  What is the need for package of  a chip? Explain about  input and output pad circuits.

8.  Write short notes on any Two:
a) Hardware/ Software co-design.
b) Chip design methodologies
c) Power optimization in CMOS circuits.

MARCH-2009 PAPER–(REGULAR)

1.a)  What are the various marks used in CMOS p-well process? What is the significance of each.
b)  Compare bipolar and CMOS technologies.

2.a)  What is threshold voltage? What are various factors that influences threshold voltage.
b)  Explain the principle of BICMOS inverter.

3.a)  What are various symbols used in sticks notation? Draw the stick diagram of CMOS inverter.
b)  What are scalable design rules? Explain.

4.  What are various switch logic circuits? Compare their merits and demerits.

5.  Explain how fan-out and path delay influences delay in combinational networks.

6. Explain about 1 -φ  clocking rules for flip-flops and  2 -φ   clocking disciplies for latches.

7.  What are various floor planning methods? Explain them clearly.

8.  Write short notes on any Two:
a) Testing of sequential circuits
b) Hardware/software co-design.
c) Combinational gates an network testing.

SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)

1.a)  What are the various processes of CMOS fabrication? Illustrate the main steps in a typical n-well process.
b)  Tabulate the comparism between CMOS and Bipolar Technologies.

2.a)  Determine the Pull-up to Pull-down ratio for an nMOS inverter driven through one or more pass transistors.
b)  Draw a simple BiCMOS inverter circuit diagram and explain its operation.

3.a)  Explain about scalable Design rules related to NMOS and CMOS Technologies.
b)  With suitable diagrams explain some switch logic arrangements.

4.a)  With neat sketches describe the various Layout Design methods.
b)  Explain the clocking Analysis related to sequential systems.

5.a)  With relevant diagrams explain about various Floorplanning methods used in Layout design.
b)  Explain the design Methodology for IBM ASICs.

6.a)  Give the device structure for CMOS inverter and explain the same.
b)  Draw Latch-up circuit model and explain its operation.

7.a)  Briefly explain an important issues in system-on-chip design.
b)  Write notes on Architecture Testing related Architecture VLSI Design.

8.  Write notes on any Two of the following:
a)  Wires and Vias
b)  Design validation and Testing.
c)  The Integrated circuit (IC) Era.

FEBRUARY-2007 PAPER

1.a)  Give advantages of CMOS over bipolar technologies
b)  Explain in detail the electrical model of a MOS transistor
c)  Discuss the BICMOS process

2.a)  What are the effects of scaling of Vt?
c)  What are the design rules? Why is metal – metal spacing larger they poly-poly spacing?

3.a)  Explain the delay in combinational logic network and how combinational delay can be reduced.
b)  Compute the zero delay signal probabilities for all signals in the network shown

4.a)  What  is  clock skew? Explain how clock skew affects the digital system. What is the maximum allowable skew for the parameters   T =10 ns, tpr = 1 ns, tsr = 1 ns, tsl = 1 ns, tpl = 5 ns, tp = 5 ns.  What is the minimum allowable clock period under these conditions?
b)  What is ATPG? DFT? Generate a set of Sequential tests for the “01” – string recognizer which test for all stuck – at – 0/1 faults, assuming you don’t know the initial state.

5.  Design a Booth Multiplier
a)  Design the logic for one bit of a adder substractor (leaf cell)
b)  Design a stick diagram for the adder substractor

6.a)  Give routing techniques to equalize channel utilization
b)  What are the problems presented by power distribution? How are they solved?
c)  Discuss the clock distribution strategies for VLSI system.
d)  How many output pads can be supported by 10λ wide power line in pad ring?

7.a)  Give a generic IC design flow chart and explain.
b)  Explain the technology independent and technology dependant strategies of logic optimization used in logic synthesis
c)  Explain briefly how the hardware/software Co-simulation and co- synthesis issued are addressed.

8.a)  How would you translate a register transfer structure into a legal 2-phase latched sequential machine?
b)  Write short notes on any two of the following:
i)  Differentiate the devices PAL, PLA and FPGA
ii) Cross-talk
iii)  Placement and routing in floor planning.

JNTU M.TECH QUESTION PAPERS | JNTU QUESTION PAPERS | M.TECH QUESTION PAPERS | MTECH VLSI TECHNOLOGY AND DESIGN QUESTION PAPERS | M.TECH VLSI QUESTION PAPERS | JNTU M.TECH PAPERS

### Similar Posts:

63 Responses

And then confirm your email subcription

### 63 Comments to “JNTU MTECH VLSI TECHNOLGY & DESIGN QUESTION PAPERS”

1. k. says:

plz send me sir….

2. swathi says:

sir i want vlsi branch all question papers.plzzzz send to my mail sir.
swathi.sareddy95@gmail.com

3. bharani says:

sir,i need mtech-vlsi-all subjects previous qsn papers of jntu,anantapur

4. anupama says:

hello sir i want 2012th question paper of VLSI technology and design of m.tech 1st sem

5. lathika reddy says:

hai friends can u forward me the material of vlsi and embedded system mtech materials plsssssssssssssssssssss to my mail id lalli6red@gmail.com

6. anuhyaluky says:

sir i want m.tech 1st sem decs(digital electronics and communication systems) 2011 previous quention papers please help me by posting this paper

7. C.Arun kumar says:

I requesting you please send me previous 3 years of all question papers of MTECH (VLSI) Ist semster to my mail.i will be very thank full if u do this favour to me.

8. prathima says:

plzzzzzzzzzzzzzz i want vlsi 1 sem quetion papers 2011

9. siva says:

10. spandu says:

sir i want previous question papers for embedded system concepts and embedded system design so i requesting you to please send it to my mail and i’m thanks you to providing other question papers

11. SARITHA says:

sir iwant previous question papers for mtech dsce

12. ppw says:

sir i need previous 3 question papers of each subject in M.Tech VLSI Design

13. bhavani says:

hi sir iwant all previous papers in ece m-tech