JNTU MTECH VLSI TECHNOLGY & DESIGN QUESTION PAPERS
JNTU M.TECH QUESTION PAPERS | JNTU QUESTION PAPERS | M.TECH QUESTION PAPERS | MTECH VLSI TECHNOLOGY AND DESIGN QUESTION PAPERS | M.TECH VLSI QUESTION PAPERS | JNTU M.TECH PAPERS
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech I Semester Examinations
VLSI TECHNOLOGY AND DESIGN
(Common To Embedded Systems, Digital Systems & Computer Electronics, VLSI
System Design and Communication Systems)
OCTOBER/NOVEMBER 2011 REGULAR EXAMINATION PAPER
1.a) Explain CMOS inverter voltage transfer characteristics with a neat diagram. What are the criteria for voltage threshold for high level and low level in inverter characteristics?
b) What is latch-up condition in CMOS circuits? How it can be eliminated. [12]
2.a) Determine the Pull-up to Pull-down ratio for an NMOS inverter driven through one or more pass transistors.
b) Explain about-NMOS logic, domino logic and DCVS logic and compare them. [12]
3.a) What are the varieties of design layout of wiring trees in the wires and delay?
b) With suitable diagrams explain some switch logic arrangements. [12]
4.a) Design the static complementary pull up and pull down networks for these expressions;
b) Draw a stick diagram for a three input NOR gate. [12]
5.a) Explain the standard cell layout design in combinational logic network.
b) Explain how the gate placement affects load capacitance in fanout of combinational logic. [12]
6.a) Explain the clocking Analysis related to sequential systems.
b) Draw and explain the cross section of a pair of stacked capacitor DRAM cell. [12]
7.a) Explain system-on-chip concept using platform based design.
b) What are the various floor-planning tips and explain it? [12]
8. Write a short note on a) High level synthesis.
b) ASM chart design [12]
SEPTEMBER-2009 PAPER–(SUPPLEMENTARY)
1.a) Explain how cost and delay of a logic gate varies with different IC technologies.
b) What are the deficiencies of MOS technology? How they can it be over come?
2.a) Explain the principle of CMOS inverter with V-I wave forms.
b) What is latch-up condition in CMOS circuits? How it can be eliminated.
3.a) What are λ -based design rules? Give them for each layer.
b) Draw the stick diagram of 2-impact Ex-or gate.
4. Explain about-nmos logic, domino logic and DCVS logic and compare them.
5.a) What are the various simulators used for combinational logic design? Explain their need.
b) What are different testing methods for testing combinational gate? Explain with an example.
6.a) Distinguish between clock skew and signal skew with an example.
b) Explain about 2-phase clouding disciplines
7.a) Explain how clock routing design optimizes the clock skew in floor planning.
b) What is the need for package of a chip? Explain about input and output pad circuits.
8. Write short notes on any Two:
a) Hardware/ Software co-design.
b) Chip design methodologies
c) Power optimization in CMOS circuits.
MARCH-2009 PAPER–(REGULAR)
1.a) What are the various marks used in CMOS p-well process? What is the significance of each.
b) Compare bipolar and CMOS technologies.
2.a) What is threshold voltage? What are various factors that influences threshold voltage.
b) Explain the principle of BICMOS inverter.
3.a) What are various symbols used in sticks notation? Draw the stick diagram of CMOS inverter.
b) What are scalable design rules? Explain.
4. What are various switch logic circuits? Compare their merits and demerits.
5. Explain how fan-out and path delay influences delay in combinational networks.
6. Explain about 1 -φ clocking rules for flip-flops and 2 -φ clocking disciplies for latches.
7. What are various floor planning methods? Explain them clearly.
8. Write short notes on any Two:
a) Testing of sequential circuits
b) Hardware/software co-design.
c) Combinational gates an network testing.
SEPTEMBER-2008 PAPER–(SUPPLEMENTARY)
1.a) What are the various processes of CMOS fabrication? Illustrate the main steps in a typical n-well process.
b) Tabulate the comparism between CMOS and Bipolar Technologies.
2.a) Determine the Pull-up to Pull-down ratio for an nMOS inverter driven through one or more pass transistors.
b) Draw a simple BiCMOS inverter circuit diagram and explain its operation.
3.a) Explain about scalable Design rules related to NMOS and CMOS Technologies.
b) With suitable diagrams explain some switch logic arrangements.
4.a) With neat sketches describe the various Layout Design methods.
b) Explain the clocking Analysis related to sequential systems.
5.a) With relevant diagrams explain about various Floorplanning methods used in Layout design.
b) Explain the design Methodology for IBM ASICs.
6.a) Give the device structure for CMOS inverter and explain the same.
b) Draw Latch-up circuit model and explain its operation.
7.a) Briefly explain an important issues in system-on-chip design.
b) Write notes on Architecture Testing related Architecture VLSI Design.
8. Write notes on any Two of the following:
a) Wires and Vias
b) Design validation and Testing.
c) The Integrated circuit (IC) Era.
FEBRUARY-2007 PAPER
1.a) Give advantages of CMOS over bipolar technologies
b) Explain in detail the electrical model of a MOS transistor
c) Discuss the BICMOS process
2.a) What are the effects of scaling of Vt?
b) Cascaded inverters can drive large capacitive loads – explain how
c) What are the design rules? Why is metal – metal spacing larger they poly-poly spacing?
3.a) Explain the delay in combinational logic network and how combinational delay can be reduced.
b) Compute the zero delay signal probabilities for all signals in the network shown
4.a) What is clock skew? Explain how clock skew affects the digital system. What is the maximum allowable skew for the parameters T =10 ns, tpr = 1 ns, tsr = 1 ns, tsl = 1 ns, tpl = 5 ns, tp = 5 ns. What is the minimum allowable clock period under these conditions?
b) What is ATPG? DFT? Generate a set of Sequential tests for the “01” – string recognizer which test for all stuck – at – 0/1 faults, assuming you don’t know the initial state.
5. Design a Booth Multiplier
a) Design the logic for one bit of a adder substractor (leaf cell)
b) Design a stick diagram for the adder substractor
6.a) Give routing techniques to equalize channel utilization
b) What are the problems presented by power distribution? How are they solved?
c) Discuss the clock distribution strategies for VLSI system.
d) How many output pads can be supported by 10λ wide power line in pad ring?
7.a) Give a generic IC design flow chart and explain.
b) Explain the technology independent and technology dependant strategies of logic optimization used in logic synthesis
c) Explain briefly how the hardware/software Co-simulation and co- synthesis issued are addressed.
8.a) How would you translate a register transfer structure into a legal 2-phase latched sequential machine?
b) Write short notes on any two of the following:
i) Differentiate the devices PAL, PLA and FPGA
ii) Cross-talk
iii) Placement and routing in floor planning.
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56 Comments to “JNTU MTECH VLSI TECHNOLGY & DESIGN QUESTION PAPERS”
hi sir i want microcontroller for embeded system design,digital system design, and advanced digital signal processing,all on previous papers september 2010 , march 2010, sept 2009, march2009, iam studying m-tech(ece) electronics and communication engineering so forward to me please
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(1.TESTING AND TESTABILITY
2.LOW POWER VLSI DESIGN
3.ALGORITHMS FOR VLSI DESIGN AUTOMATION
4FPGA ARCHITECTURE &APPLICATIONS
5SCRIPTING LANGUAGE FOR VLSI DESIGN AUTOMATION
6.REAL TIME OPERATING SYSTEMS)
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advanced mathematics for communication systems
modern digital communication techniques
computer communication networks
information coding &techniques
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radar signal processing
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the subjects are:
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2.ANALOG AND DIGITAL INTEGRATED CIRCUITS DESIGN
3.EMBEDDED SYSTEM DESIGN
4.EMBEDDED SYSTEM CONCEPTS
5.DIGITAL SYSTEM DESIGN
6. VHDL MODELLING OF DIGITAL SYSTEMS
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2.embedded real time operatinfg systems
3.advanced digital signal processing
4.micro controller of embeddeb systems
Thank you
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3.device modelling
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6.dsp and thier solution
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ADSP
CODING THEORY AND PRACTICE
DETECTION AND ESTIMATION OF SIGNALS
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sir i need JNTU Mtech VLSI 2nd semester previous question papers for the following Subjects
1) Algorithms for VLSI design
2)cpld & fpga
3) Embedded Real time Operating Sytem
4) Low Power Design
5) Design of fault tolerant systems
6) DSP processors and architectures
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sir i need JNTU Mtech VLSI 2nd semester previous question papers for the following Subjects
1) Algorithms for VLSI design
2)cpld & fpga
3) Embedded Real time Operating Sytem
4) Low Power Design
5) Design of fault tolerant systems
6) DSP processors and architectures
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sir i need JNTU Mtech VLSI 2nd semester previous question papers for the following Subjects
1) System on Chip Architecture
2) CMOS Analog & Mixed Signal Design
3) Embedded Real time Operating Sytem
4) Low Power Design
5) Design of fault tolerant systems
6) dsp processors and architectures
need JNTU Mtech VLSI 2nd semester previous question papers for the following Subjects
1) System on Chip Architecture
2) CMOS Analog & Mixed Signal Design
3) Embedded Real time Operating Sytem
4) Low Power Design
5) Design of fault tolerant systems
6) dsp processors and architectures
sir pls send me previous question papers on CMOS Analog & Mixed Signal Design.as soon as possible because iof urgent requirement of it
need JNTU Mtech VLSI 2nd semester previous question papers for the following Subjects
1) System on Chip Architecture
2) CMOS Analog & Mixed Signal Design
3) Embedded Real time Operating Sytem
4) Low Power Design
5) Design of fault tolerant systems
6) dsp processors and architectures
need JNTU Mtech VLSI 2nd semester previous question papers for the following Subjects
1) System on Chip Architecture
2) CMOS Analog & Mixed Signal Design
4) Embedded Real time Operating Sytem
5) Low Power Design
6) Design of fault tolerant systems
7) dsp processors and architectures
need JNTU Mtech VLSI 2nd semester previous question papers for the following Subjects
1) System on Chip Architecture
2) CMOS Analog & Mixed Signal Design
4) Embedded Real time Operating Sytem
5) Low Power Design
6) Design of fault tolerant systems
7) dsp processors and architectures
I need JNTU Mtech VLSI 2nd semester previous question papers for the following Subjects
1) System on Chip Architecture
2) CMOS Analog & Mixed Signal Design
4) Embedded Real time Operating Sytem
5) Low Power Design
6) Design of fault tolerant systems
7) VLSI signal processing
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Hi dude
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i searched but cant able to find those question papers
and cpld fpga questions also
waiting for your reply
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thnks for posts….
please post 2010 papers as early as pble…
sir will u ple provide me the solutions for some problems regading clock skew,sequential cirxcuit testing……. i am waiting for ur reply
pls provide mtech (embedded systm) previous question papers of all subjects like vlsi,dsd,adsp/ertos/
pls provide mtech(vlsi) previous question papers of all subjects
Thanq sir for providing m.tech questionpapers for (DSCE)didital systems and computer electronics.sir pls provide the questionpapers for (Microcontrollers for embedded system Design),advanced digital signal processing)$Internetworking.pls provide this papers to my mail id sir sphanindhar@gail.com
Thanq sir for providing m.tech questionpapers for (DSCE)didital systems and computer electronics.sir pls provide the questionpapers for (Microcontrollers for embedded system Design),advanced digital signal processing)$Internetworking.pls provide this papers to my mail id sir .prasadvemulas@gmail.com.
thank u sir for providing mtech vlsi papers…pls provide d papers for other subjects of VLSI System Design…